1. Field
The following description relates to a technology of achieving efficient access to a multiple bank memory in a computing apparatus.
2. Description of the Related Art
A processor, in particular, a digital signal processor may provide enhanced performance by accessing a multiple bank memory through a multi-core structure and a multi-port structure. In general, a multiple bank memory stores data in a word unit including 4 bytes. For example, a plurality of pieces of data may have a series of address values. For example, a first word corresponding to the first 4 bytes is stored in the first bank, and a second word corresponding to the second 4 bytes is stored in the second bank. A request for the first 4 bytes or the second 4 bytes is implemented through an access to a single bank. Such memory access is referred to as aligned memory access. However, in order to access a word including the second byte to fifth byte, both of the first bank and the second bank need to be accessed. Such memory access is referred to as unaligned memory access.
If an unaligned memory access occurs in a system adopting a single bank memory architecture, the memory access needs to be performed twice. In a system adopting a multi-port and multi-bank memory architecture, two banks can be simultaneously accessed through a memory controller, thereby achieving an unaligned memory access having the same memory latency as that of an aligned memory access. However, when a system has two ports and two banks, if one port accesses the two banks, the remaining port can not access any of the banks, failing to bring out any advantage for the multi port system.